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Multiprocessor system with selective processor power down of core and inter-processor communications ports
Multiprocessor system with selective processor power down of core and inter-processor communications ports
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机译:多处理器系统,可选择性关闭核心和处理器间通信端口的处理器电源
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摘要
The present invention provides a multiprocessor system and method in which power can be withheld from a core and inter-processor communications ports of a first processor while power continues to be supplied to a second processor.
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