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Gate array integrated circuit including a unit cell basic layer having gate terminal regions allowing two contact pads to be disposed laterally
Gate array integrated circuit including a unit cell basic layer having gate terminal regions allowing two contact pads to be disposed laterally
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机译:门阵列集成电路,其包括具有栅端子区域的单位单元基本层,该栅端子区域允许两个接触焊盘横向布置
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摘要
A gate array integrated circuit forming part of a semiconductor integrated circuit includes a basic layer of a unit cell in which a PMOS and an NMOS transistor are connected with a poly-silicon strip. The poly-silicon strip has gate terminal regions formed to laterally extend to allow two or more contact pads or through-holes to be disposed in each gate terminal region. It is thus possible to improve wiring efficiency and also micro-miniaturization and yield of the gate array integrated circuit. A layout method for a gate array integrated circuit is also provided.
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