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Method of searching paths suffering from the electrostatic discharge in the process of an integrated circuit design

机译:在集成电路设计过程中寻找遭受静电放电的路径的方法

摘要

A method of searching paths that are susceptible to electrostatic discharge (ESD) at the beginning of an integrated circuit (IC) design is disclosed that includes a circuit spreading out algorithm, a matrix closure algorithm, and a supernode algorithm. The found paths are required to satisfy conditions including that (a) they are connected from a gate of a transistor to a source or a drain thereof, and (b) the head node and the tail node of each path are pins of a top level of the IC. −1/0/1 matrix multiplication is employed by both the circuit spreading out algorithm and the matrix closure algorithm so as to obtain a result of node connections after a plurality of matrix self-multiplications.
机译:公开了一种在集成电路(IC)设计开始时搜索容易受到静电放电(ESD)影响的路径的方法,该方法包括电路扩展算法,矩阵闭合算法和超节点算法。找到的路径需要满足以下条件:(a)它们从晶体管的栅极连接到其源极或漏极,并且(b)每个路径的头节点和尾节点是顶层的引脚IC的。电路扩展算法和矩阵闭合算法均采用-1/0/1矩阵乘法,以便在多次矩阵自乘法之后获得节点连接的结果。

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