DELTA SIGMA MODULATOR ANALOG-TO-DIGITAL CONVERTERS WITH QUANTIZER OUTPUT PREDICTION AND COMPARATOR REDUCTION

摘要

The quantizers of delta sigma modulators in the signal processing systems described herein use a reduced set of comparators for quantization by predetermining and maintaining a maximum per cycle deviation d between a loop filter output signal VSUBLF/SUB(t) and a predicted quantizer output signal qSUBest/SUB. In at least one embodiment, a maximum quantizer level deviation d is defined in terms of a number of quantization levels. Thus, the number of comparators in a quantizer needed to quantize the quantizer input signal VSUBin/SUB(t) is based on the maximum quantizer level deviation d. In addition to using fewer comparators than available quantization output levels N, the quantizers can use an even number of comparators M, in contrast to comparable conventional reduced comparator ADC tracking quantizer designs using M+1 number of comparators, where N and Mare integers and M N.