IMPROVED SENSING CAPACITANCE IN COLUMN SAMPLE AND HOLD CIRCUITRY IN A CMOS IMAGER AND IMPROVED CAPACITOR DESIGN

摘要

Improved designs for a capacitor, and particularly the sensing and references capacitors used In a column sampl-and-hold circuitry in a CMOS imager, are disclosed that minimize layout area In one embodiment, an additional plate layer (e g, formed in metal 1) is provided above the traditional poly 2-poly 1 capacitor, which additional plate is shorted to traditional poly 1 bottom plate This adds an additional area capacitance (CaI) which Is additive to the capacitance formed by the poly 2-poly 1 capacitor (Cp) to increase the total capacitance, which thus allows the capacitor to be made smaller in layout area In another embodiment, an additional piece of metal 1 contacts the poly 2 top capacitor plate, such that a sidewall capacitance Is defined between the sidewalls of the metal 1 pieces, which is again additive to the total capacitance These sidewalls can be interdigitized to increase the area of the sidewall capacitance.