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THIN FILM RESISTOR HEAD STRUCTURE AND METHOD FOR REDUCING HEAD RESISTIVITY VARIANCE

机译:薄膜电阻器头部结构及减小头部电阻率方差的方法

摘要

A method of making an integrated circuit thin film resistor includes forming a first dielectric layer (18B) over a substrate and providing a structure to reduce variation of head resistivity thereof by forming a dummy fill layer (9A) on the first dielectric layer, and forming a second dielectric layer (18D) over the first dummy fill layer. A thin film resistor (2) is formed on the second dielectric layer (18D). A first inter-level dielectric layer (21A) is formed on the thin film resistor and the second dielectric layer. A first metal layer (22A) is formed on the first inter-level dielectric layer and electrically contacts a portion of the thin film resistor. Preferably, the first dummy fill layer is formed as a repetitive pattern of sections such that the repetitive pattern is symmetrically aligned with respect to multiple edges of the thin-film resistor (2). Preferably, the first dummy fill layer is formed so as to extend sufficiently far beyond ends of the thin-film resistor to ensure only a negligible amount of systematic resistance error due to misalignment.
机译:一种制造集成电路薄膜电阻器的方法,包括在基板上形成第一介电层(18B),以及通过在第一介电层上形成虚拟填充层(9A)来提供减小其头部电阻率变化的结构,以及形成在第一虚拟填充层上方的第二介电层(18D)。在第二介电层(18D)上形成薄膜电阻器(2)。在薄膜电阻器和第二电介质层上形成第一层间电介质层(21A)。第一金属层(22A)形成在第一层间电介质层上并且电接触薄膜电阻器的一部分。优选地,第一虚拟填充层形成为部分的重复图案,使得该重复图案相对于薄膜电阻器(2)的多个边缘对称地对准。优选地,第一虚设填充层形成为足够远地延伸超过薄膜电阻器的端部,以确保仅由于可对准而导致的系统电阻误差可忽略不计。

著录项

  • 公开/公告号EP1872389A1

    专利类型

  • 公开/公告日2008-01-02

    原文格式PDF

  • 申请/专利权人 TEXAS INSTRUMENTS INCORPORATED;

    申请/专利号EP20060750034

  • 发明设计人 BEACH ERIC W.;STEINMANN PHILIPP;

    申请日2006-04-10

  • 分类号H01L21/20;

  • 国家 EP

  • 入库时间 2022-08-21 19:57:21

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