CLOCK GENERATION CIRCUIT, CONTROL METHOD OF CLOCK GENERATION CIUCUIT, CLOCK REPRODUCING CIRCUIT, SEMICONDUCTOR MEMORY DEVICE, AND DYNAMIC RANDOM ACCESS MEMORY

摘要

A DLL circuit or the like is configured so as to be capable of measuring the optimum number of cycles for a delay amount from the input of an external clock to the output of data through the use of a variable delay circuit and performing lock according to the measured number of cycles, whereby a clock generation circuit having a wide lock range can be implemented regardless of the performance of the variable delay circuit and a clock access time.