VITERBI DECODER ARCHITECTURE FOR USE IN SOFTWARE-DEFINED RADIO SYSTEMS

摘要

A Viterbi decoder architecture for use in a software-defined radio system is provided to implement optimization for the maximum data transmission rate and different ranges of data transmission rate. A Viterbi decoder includes a branch metric calculation block(405), an ACS(Add-Compare-Select) and path metric calculation block(410), a trellis and traceback calculation block(415), a current stage memory buffer(420), a next stage memory buffer(425), a control logic and registers block(430), and an AGU(Address Generation Unit)(435). The reconfigurable Viterbi decoder is connected with a memory(350). The memory is logically divided into a shared input symbol buffer(360) and a shared trails history buffer(370).