Memory device, memory module, processor system and method of operating a memory device for synchronized write data on a high speed memory bus

摘要

Some of the synchronous semiconductor memory device accepts the command buffer and clock light that are not clock buffer. Meanwhile, the write command in synchronization with the clock associated with the command is a write data in synchronization with the write clock. Any phase shift may exist between the command clock and the clock light due to the use of a buffer. The presence of a phase shift between these two clock is difficult to determine when the memory device accepts only deulyeoya the write data associated with the write command. Synchronous memory device according to the present invention uses a conventional strobe signal is a three state buffer that is not light during a pragma for indicating the start of the write data. Before applying the program flag signal to the loop lag detection simply it can be a preamble signal applied to the strobe signal line. ; Synchronization, memory, a clock light, the command clock, phase shift, pragma, preamble