SEMICONDUCTOR MEMORY DEVICE HAVING INPUT LATENCY CONTROL CIRCUIT AND METHOD OF CONTROLLING INPUT LATENCY OF THE SAME

摘要

Wave latency control input method for a semiconductor memory device and a semiconductor memory device including an input latency control circuit that is controlled in a pipelined manner is disclosed. The semiconductor memory device includes a clock buffer, the command decoder, and the input latency control circuit. Latency input control circuit generates an internal clock signal, the write command signal, and a write latency signal, the address signal wave gating in a pipelined manner, and column address signals, bank address signals based on. A semiconductor memory device having an input latency control circuit can increase the margin between the can reduce the number of the flip-flop input control signals and valid address signals needed for latency control, a semiconductor integrated circuit low power consumption to take up less area when implemented.