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A phase locked loop including switched-capacitor-network operated by the output clock of the voltage controlled oscillator and the method of control the phase locked loop
A phase locked loop including switched-capacitor-network operated by the output clock of the voltage controlled oscillator and the method of control the phase locked loop
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机译:包括由压控振荡器的输出时钟操作的开关电容器网络的锁相环及其控制方法
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摘要
A phase locked loop using a switched-capacitor-network operated by an output clock of a voltage controlled oscillator and a control method thereof are provided to decrease a size of the PLL(Phase Locked Loop) by generating a large resistance using a small-sized capacitor. A phase/frequency detector(210) compares phases of a reference signal and a feedback signal with each other and generates an up or down signal according to whether the reference signal leads the feedback signal or not. A first charge pump(220) outputs a first pumping signal according to the up or down signal. A second charge pump(230) outputs a second pumping signal according to the up or down signal. A delay unit(240) delays the second pumping signal according to a divided clock and outputs a delay signal. A loop filter(250) integrates over the first pumping signal and the delay signal and outputs a control voltage. A VCO(Voltage Controlled Oscillator)(260) outputs an output clock according to the control voltage. A first divider circuit(270) divides the output clock and generates a divided clock. A second divider circuit(280) divides the output clock and generates the feedback signal.
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