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A phase locked loop including switched-capacitor-network operated by the output clock of the voltage controlled oscillator and the method of control the phase locked loop

机译:包括由压控振荡器的输出时钟操作的开关电容器网络的锁相环及其控制方法

摘要

A phase locked loop using a switched-capacitor-network operated by an output clock of a voltage controlled oscillator and a control method thereof are provided to decrease a size of the PLL(Phase Locked Loop) by generating a large resistance using a small-sized capacitor. A phase/frequency detector(210) compares phases of a reference signal and a feedback signal with each other and generates an up or down signal according to whether the reference signal leads the feedback signal or not. A first charge pump(220) outputs a first pumping signal according to the up or down signal. A second charge pump(230) outputs a second pumping signal according to the up or down signal. A delay unit(240) delays the second pumping signal according to a divided clock and outputs a delay signal. A loop filter(250) integrates over the first pumping signal and the delay signal and outputs a control voltage. A VCO(Voltage Controlled Oscillator)(260) outputs an output clock according to the control voltage. A first divider circuit(270) divides the output clock and generates a divided clock. A second divider circuit(280) divides the output clock and generates the feedback signal.
机译:提供一种使用由压控振荡器的输出时钟操作的开关电容器网络的锁相环及其控制方法,以通过使用小尺寸产生大电阻来减小PLL(锁相环)的尺寸。电容器。相位/频率检测器(210)将参考信号和反馈信号的相位相互比较,并根据参考信号是否领先反馈信号来产生上或下信号。第一电荷泵(220)根据上升或下降信号输出第一泵浦信号。第二电荷泵(230)根据上升或下降信号输出第二泵浦信号。延迟单元(240)根据分频后的时钟延迟第二泵浦信号并输出​​延迟信号。环路滤波器(250)对第一泵浦信号和延迟信号进行积分并输出控制电压。 VCO(电压控制振荡器)(260)根据控制电压输出输出时钟。第一分频器电路(270)对输出时钟进行分频并生成分频时钟。第二分频器电路(280)对输出时钟进行分频并产生反馈信号。

著录项

  • 公开/公告号KR100830898B1

    专利类型

  • 公开/公告日2008-05-22

    原文格式PDF

  • 申请/专利权人

    申请/专利号KR20060089617

  • 发明设计人 조성환;하소명;

    申请日2006-09-15

  • 分类号H03L7/099;H03L7/08;

  • 国家 KR

  • 入库时间 2022-08-21 19:52:07

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