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Self aligned method of forming a semiconductor memory array of floating gate memory cells with low resistance source regions and high source coupling, and a memory array made thereby
Self aligned method of forming a semiconductor memory array of floating gate memory cells with low resistance source regions and high source coupling, and a memory array made thereby
The invention, in a semiconductor substrate having an isolation region and an active region a plurality of spaced apart on the parallel substrates with each other substantially in a column direction, to a self-aligned method for forming a semiconductor memory array of floating gate memory cells. Floating gates are formed in each of the active regions. In the row direction, trenches are formed that include indents or different widths. Trenches, disposed adjacent to the floating gate, but the conductive material to form blocks of conductive material constituting a source region disposed over the floating gate and the first portion being insulated from the floating gate but with a second portion being insulated from the floating gate filled with. ; Isolation, the floating-gate, self-aligned trench, the conductive material
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