首页> 外国专利> Self aligned method of forming a semiconductor memory array of floating gate memory cells with low resistance source regions and high source coupling, and a memory array made thereby

Self aligned method of forming a semiconductor memory array of floating gate memory cells with low resistance source regions and high source coupling, and a memory array made thereby

机译:自对准形成具有低电阻源区和高源耦合的浮栅存储单元的半导体存储阵列的方法,以及由此制成的存储阵列

摘要

The invention, in a semiconductor substrate having an isolation region and an active region a plurality of spaced apart on the parallel substrates with each other substantially in a column direction, to a self-aligned method for forming a semiconductor memory array of floating gate memory cells. Floating gates are formed in each of the active regions. In the row direction, trenches are formed that include indents or different widths. Trenches, disposed adjacent to the floating gate, but the conductive material to form blocks of conductive material constituting a source region disposed over the floating gate and the first portion being insulated from the floating gate but with a second portion being insulated from the floating gate filled with. ; Isolation, the floating-gate, self-aligned trench, the conductive material
机译:自对准方法用于形成浮栅存储单元的半导体存储阵列的自对准方法,在具有隔离区和有源区的半导体衬底中,所述隔离区和有源区在平行衬底上基本上在列方向上彼此间隔开。在每个有源区中形成浮栅。在行方向上,形成包括凹痕或不同宽度的沟槽。沟槽,邻近于浮栅设置,但是导电材料形成导电材料块,该导电材料块构成布置在浮栅上方的源极区域,并且第一部分与浮栅绝缘,但是第二部分与浮栅绝缘用。 ;隔离,浮栅,自对准沟槽,导电材料

著录项

  • 公开/公告号KR100855885B1

    专利类型

  • 公开/公告日2008-09-03

    原文格式PDF

  • 申请/专利权人

    申请/专利号KR20010058313

  • 发明设计人 레비아미태이;왕치신;

    申请日2001-09-20

  • 分类号H01L27/115;H01L21/8247;

  • 国家 KR

  • 入库时间 2022-08-21 19:51:39

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