DEVICE FOR SIMULATION SUBSYSTEM HR ALARM

摘要

The utility model to simulate operation of frame synchronization subsystem uses to establish frame synchronization synchronization sequence consisting of several sequences set type with adjustable tripping threshold circuit and synchronization sequence form. The register block with the reference synchronization sequence contains sequences 1, divided into parts, which by means of the multiplexer 2 are supplied to a comparator 3. The comparator 3 compares the reference synchronization sequence units with data supplied to the information input of the comparator 3. The pulse counter 11 performs the timer function to control and controlling the operation of the circuit. By changing the combination of the inputs of the first 4 elements, and fourth 13 element D and the fifth 16 of AND standing on the comparator output of register 3 may configure thresholds circuit when receiving parts of the reference synchronization sequence, and altering the register unit registers the content to the reference sequences 1, changing the length and structure synchronization sequence. Thus, it is possible to simulate reception timing varying lengths and structures with different levels of error and lock signal passes false positives circuit.