The dram - output circuits for the support of the sequential data acquisition for the reduction of the core access times

摘要

Described are the memory system (200) designed to emphasize differences between memory-cell access times. As a consequence of these access-time variations, data read from different memory cells (120) arrives at some modified output circuitry (205). The output circuitry (205) sequentially offloads the data in the order of arrival. Data access times are reduced because the output circuitry (205) can begin shifting the first data to arrive before the slower data is ready for capture. Differences between data access times for cells (120) in a given memory array (115) may be emphasized using differently sized sense amplifiers (210, 215), routing, or both.