A semiconductor memory device having the ability of a totzykluslosschreiboperation either one or two cycles after the receipt of a write operation to carry out

摘要

PURPOSE: A semiconductor memory device is provided to perform a write operation after one cycle and two cycle without a dead cycle. CONSTITUTION: The semiconductor memory device comprises an address input control part(26, 28, 30), a data input control part(34, 36, 38) and a data transfer control part(40). The address input control part(26, 28, 30) delays and outputs a write address by one cycle at a write operation after one cycle, and the write address by two cycles at a write operation after two cycle. The data input control part(34, 36, 38) delays and outputs write data inputted after one cycle by zero cycle and one cycle at the write operation after one cycle, and delays and outputs write data inputted after two cycles by zero cycle, one cycle and two cycles at the write operation after two cycle. When performing the write operation after one cycle, the data transfer control part(40) transfers the data delayed by zero cycle when two write commands are sequentially inputted, and the transfers data delayed by one cycle when a read command and a write command are sequentially inputted. When performing the write operation after two cycles, the data transfer control part(40) transfers the data delayed by zero cycle when two write commands are sequentially inputted, and transfers the data delayed by one cycle when either a write command, a read command and a write command or a read command and two write commands are sequentially inputted, and transfers the data delayed by two cycles when two read commands and a write command are sequentially inputted.