Logic signal's i.e. clock signal, parasite acceleration detecting method for integrated circuit of e.g. chip card, involves determining acceleration when check bits do not have their respective initial or inversed values, simultaneously

摘要

The method involves determining two check bits (QA, QB), and providing two initial values to the check bits, respectively. The value of the check bit (QA) is inversed after a delay (DLY1), and the value of the check bit (QB) is inversed after a delay (DLY2) at each of determined variation fronts of a logic signal i.e. clock signal (CK), where the latter delay is lesser than the former delay. Acceleration of the signal is determined when the check bits do not have their respective initial values or inversed values, simultaneously. An independent claim is also included for a device for detecting acceleration of a logic signal.