Video processing hardware architecture for video conferencing

摘要

A video processing hardware architecture for a multipoint control unit (MCU) is presented wherein a motherboard 20 carries a field programmable gate array (FPGA) connected to a plurality of additional video signal processors. These additional processors, illustrated by daughterboards 22, are interconnected with a plurality of high bandwidth (ie / 3Gb/s) links 26. Each daughterboard typically comprises a field programmable gate array (FPGA) (32, figure 4) and four digital signal processors (DSP) (28, figure 4). Also provided are stream processors P (36, figure 4) which may carry out compression, composition, motion compensation, encoding and other operations, which removes some of the processing load from other DSPs 28, and avoids using up available bandwidth by passing data between processors. The hardware architecture presented ensures that data processing is ideally performed by local DSPs thereby avoiding local bottlenecks, and where necessary, data may be moved in an efficient manner using the high bandwidth links. This architecture is particularly suited to video conferencing systems wherein the MCU is required to provide different content to each participant, dependent upon the capabilities of their local equipment. This overcomes the disadvantage of present MCUs which lack the processing capability or internal bandwidth availability to meet these processing-intensive demands. By processing the data internally using intelligent multicasting decision, intelligent scaling and compression decisions and acknowledging that the video data may be compressed without loss of visual quality, processing and bandwidth requirements may be met.