Reducing data hazards by counting the number of long-latency instructions in the thread still being processed before running the hazard instruction

摘要

Disclosed is a method for processing threads in a pipelined processor. The threads are a series of instructions, some are short-latency instructions and some are long-latency instructions and at least one is a hazard instruction, ie can cause a data hazard such as read after write or write after read. The hazard being cased by a preceding instruction needing to be processed before the hazard instruction is processed. The method has the steps of: a) before processing a long-latency instruction, adding one to a counter associated with the thread; b) after a long-latency instruction has been processed, taking one from the counter, and; c) before processing a hazard instruction, checking the value of the counter associated with the thread. If the counter is zero, the hazard instruction is processed or if the counter is non-zero, the hazard instruction is paused until later. For systems with multiple threads each thread may have its own counter. The counters may be periodically checked and if zero the thread and the hazard instruction processing is resumed.