METHOD AND SYSTEM FOR EFFICIENTLY USING MULTI-SOURCE NETWORK OF CONTROL LOGIC TO ACHIEVE TIMING CLOSURE IN CLOCKED LOGIC CIRCUIT

摘要

PPROBLEM TO BE SOLVED: To provide a method, system, and computer program product, for achieving timing closure in a clocked logic circuit. PSOLUTION: For each local clock buffer in a set of local clock buffers, a logic synthesis tool determines a clock control signal input from a set of clock control signal inputs that will drive a clock control signal to the local clock buffer at a target frequency such that a first timing constraint may be met. The operation performed by the logic synthesis tool forms a determined clock control signal input. Responsive to the logic synthesis tool determining the determined clock control signal input, the logic synthesis tool couples the local clock buffer to the determined clock control signal input that drives the clock control signal to the local clock buffer at the target frequency to achieve timing closure in the clock driven logic circuit. PCOPYRIGHT: (C)2009,JPO&INPIT