Systematic and stochastic error detection and recovery in the processing stage of the integrated circuit

摘要

The integrated circuit, each of the processing stages including a plurality (1024) comparator (1016), a delay element and a signal input (1018), (1014), no delayed signal acquisition processing logic element is included. (1016) captures the output processing logic circuit from (1014) to the non-delayed capture time delay-free signal acquisition element. In addition, the delay time of incorporation then, delayed signal acquisition element (1018), captures the value from the (1014) the processing logic. Error correction circuit and the (1026) error detection circuit (1028), it detects and corrects the stochastic error of the delay value, supply comparator (1024) the error check settled delay value. Compare the non-delay value and error checking already delay value, if they are not equal, this, and that, the incorporation of non-delay value is too early, comparator (1024) is, should be replaced by the error check settled delay value I show that is. And is transmitted to the subsequent treatment stage immediately after the incorporation, no delay value, the subsequent processing logic correct signal value and in response, with an error recovery mechanism, gate the clock before restarting the clock Suppress processing misuse such passing, the subsequent processing stages, resulting. Operating parameters clock frequency, operating voltage, the body bias voltage, temperature, etc., of the integrated circuit is adjusted in a way that enhances the overall performance, so as to maintain an error rate of non-zero finite.