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3-valued logic inverter circuit

机译:三值逻辑反相器电路

摘要

PPROBLEM TO BE SOLVED: To provide a three-valued logic inverter circuit which can be constituted of a small number of MOS and can obtain excellent characteristics. PSOLUTION: The substrate terminals of MOSep1, gp2, bp3 are connected with a first substrate voltage, the substrate terminals of MOS of MOSbn1, bn2, gn3 are connected with a second substrate voltage, the source side of MOSep1, bp3 is connected with a first signal voltage, and the source side of MOSbn1, bn2 is connected with a second signal voltage. Furthermore, the source side of MOSgn3 is connected with a third signal voltage, the source side of the MOSgp2 is connected to the drain side of the MOSbp3, and the drain side of the MOSgp2 or MOSbn2 serves as the output node. PCOPYRIGHT: (C)2008,JPO&INPIT
机译:

要解决的问题:提供一种三值逻辑反相器电路,该电路可以由少量的MOS构成并且可以获得优异的特性。

解决方案:MOSep1,gp2,bp3的基板端子与第一基板电压连接,MOSbn1,bn2,gn3的MOS基板端子与第二基板电压连接,MOSep1,bp3的源极侧连接MOSbn1,bn2的源极侧具有第一信号电压,第二源极具有第二信号电压。此外,MOSgn3的源极侧连接有第三信号电压,MOSgp2的源极侧连接至MOSbp3的漏极侧,并且MOSgp2或MOSbn2的漏极侧用作输出节点。

版权:(C)2008,日本特许厅&INPIT

著录项

  • 公开/公告号JP4318700B2

    专利类型

  • 公开/公告日2009-08-26

    原文格式PDF

  • 申请/专利权人 中村 和人;

    申请/专利号JP20060183403

  • 发明设计人 中村 和人;

    申请日2006-07-03

  • 分类号H03K19/20;H03K17/30;

  • 国家 JP

  • 入库时间 2022-08-21 19:41:04

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