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Information processing apparatus and clock automatic tuning control system clock and automatic tuning

机译:信息处理设备和时钟自动调谐控制系统时钟和自动调谐

摘要

PROBLEM TO BE SOLVED: To enable exhition of system performance to the utmost by reducing labor to be required for clock tuning and assuring only an operation margin to be required, at actual operation. ;SOLUTION: A data pattern generated by a data pattern generating circuit 120 of a constituted device 100 on the transmitting side is transmitted to a data bus 312 through transmission latches 102-1 to 102-n, data transfer from the constituted device 100 to a constituted device 200 is verified, based on the data pattern from the constituted device 100 received by reception latches 203-1 to 203-n by a data pattern verifying circuit 260 of the constituted device 200 on the receiving side and a phase of the clock for the transmission latches 102-1 to 102-n and the phase of the clock for the reception latches 203-1 to 203-n are adjusted so that the data transfer from the constituted device 100 to the constituted device 200 is performed within a prescribed number of clock cycles according to a verification result by a clock automating tuning control circuit 400.;COPYRIGHT: (C)2001,JPO
机译:要解决的问题:通过减少时钟调整所需的劳力并确保在实际操作中仅需要一个操作余量,来最大程度地发挥系统性能。 ;解决方案:由构成设备100在发送侧的数据模式生成电路120生成的数据模式通过传输锁存器102-1至102-n被传输到数据总线312,数据从构成设备100传输到存储器100。在接收侧,由构成设备200的数据模式验证电路260基于由接收锁存器203-1至203-n接收的来自构成设备100的数据模式,对构成设备200进行验证,并确定时钟的相位。调整发送锁存器102-1至102-n以及用于接收锁存器203-1至203-n的时钟的相位,以使得在规定数量内执行从构成设备100到构成设备200的数据传输。时钟自动调谐控制电路400根据验证结果确定时钟周期数; COPYRIGHT:(C)2001,JPO

著录项

  • 公开/公告号JP4227262B2

    专利类型

  • 公开/公告日2009-02-18

    原文格式PDF

  • 申请/专利权人 富士通株式会社;

    申请/专利号JP19990289016

  • 发明设计人 ▲吉▼村 勝義;山口 和枝;

    申请日1999-10-12

  • 分类号H04L7/02;G06F1/10;G06F13/42;

  • 国家 JP

  • 入库时间 2022-08-21 19:37:47

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