首页>
外国专利>
System and Method to Facilitate Deterministic Testing of Data Transfers between Independent Clock Domains on a Chip
System and Method to Facilitate Deterministic Testing of Data Transfers between Independent Clock Domains on a Chip
展开▼
机译:有助于对芯片上独立时钟域之间的数据传输进行确定性测试的系统和方法
展开▼
页面导航
摘要
著录项
相似文献
摘要
A system and method of deterministically transferring data across a first clock domain to a second clock domain includes receiving a resynchronize command, initiating a corresponding one of a plurality of read delays in each one of a second plurality of devices in the second clock domain, counting down the plurality of read delays to zero, receiving a training pattern after the plurality of read delays count down to zero in each one of the second plurality of devices, recovering a clock data in each of the second plurality of devices, receiving a synch byte by each of the second plurality of devices, selecting one of a plurality of serial lanes as a reference lane, wherein the plurality of serial lanes couple the first clock domain to the second clock domain, initiating a write pointer, writing n bytes of serial data to a buffer and converting the n bytes of data from serial data to parallel data in a serial to parallel converter such that the serial n byte data in the buffer are aligned in time.
展开▼