METHOD AND SYSTEM FOR A NON-VOLATILE MEMORY WITH MULTIPLE BITS ERROR CORRECTION AND DETECTION FOR IMPROVING PRODUCTION YIELD

摘要

A method and system for a non-volatile memory (NVM) with multiple bits error correction are provided and may include detecting bit errors in a memory element, of a NVM array integrated within a chip, which remain uncorrected after forward error correction. A redundant memory element may be utilized when the errors may be detected utilizing a cyclic redundancy check, may be within the NVM array, and may include secure information. Access to the secure information and/or the chip may be disabled when the errors are detected. The FEC operation may include one or both of an error location operation and a correction operation. The errors may be corrected when a location may be known to include the errors. The NVM array may be partitioned into regions. At least one of the redundant memory elements may be substituted in place of the memory element based on a substitution priority.