首页>
外国专利>
TIMING ANALYSIS APPARATUS AND METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT IN CONSIDERATION OF POWER SUPPLY AND GROUND NOISES
TIMING ANALYSIS APPARATUS AND METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT IN CONSIDERATION OF POWER SUPPLY AND GROUND NOISES
展开▼
机译:考虑电源和地噪声的半导体集成电路时序分析装置和方法
展开▼
页面导航
摘要
著录项
相似文献
摘要
In a timing analysis apparatus for use in a semiconductor integrated circuit, which analyzes operation timing of a semiconductor integrated circuit having a logic gate circuit including a plurality of logic gates, a controller detects at least one of a power supply voltage and a ground voltage of a power supply, decomposes the noise waveform into frequency components, classifies the frequency components into low-frequency components lower than a predetermined threshold frequency and high-frequency components higher than the threshold frequency, calculates a static delay time of each of the logic gates due to the low-frequency components, calculates a dynamic delay time of each of the logic gates due to the high-frequency components, and determines a delay time of each of the logic gates by synthesizing the calculated respective delay times.
展开▼