MULTI-FPGA PCI EXPRESS X16 ARCHITECTURE

摘要

An architecture for providing data communication between a plurality of field-programmable gate arrays (FPGAS) and a multi-channel data bus comprises a plurality of FPGAs, a switching element, and a multi-channel data bus. Each FPGA includes a multi-channel endpoint component to enable communication with at least a portion of the multi-channel data bus. The switching element couples each FPGA endpoint component with the multi-channel data bus, allowing communication between the FPGA endpoint components and the data bus such that every channel of the data bus is coupled to a channel of an FPGA endpoint component.