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Digital background correction of nonlinear error ADC's

机译:非线性误差ADC的数字背景校正

摘要

The invention provides circuits and methods for estimating and correcting nonlinear error in analog to digital converters that is introduced by nonlinear circuit elements, for example one or more residue amplifiers in a pipelined analog to digital converter integrated circuit. In a preferred method of the invention, pseudo random calibration sequences are introduced into the digital signal to be converted by a flash digital to analog converter in one or more initial stages of the pipelined analog to digital converter circuit. A digital residue signal of the output of the one or more initial pipelined analog to digital converter stages is sampled. Intermodulation products of the pseudo random calibration sequences that are present in the digital residue signal are determined to estimate nonlinear error introduced by the residue amplifier in the one or more stages. A digital correction signal is provided to the output of the one or more stages to cancel estimated nonlinear error.
机译:本发明提供了用于估计和校正模数转换器中的非线性误差的电路和方法,该电路和方法是由非线性电路元件(例如流水线模数转换器集成电路中的一个或多个残差放大器)引入的。在本发明的一种优选方法中,在流水线式模数转换器电路的一个或多个初始阶段中,将伪随机校准序列引入要由闪存数模转换器转换的数字信号中。采样一个或多个初始流水线模数转换器级的输出的数字残差信号。确定存在于数字残差信号中的伪随机校准序列的互调产物,以估计残差放大器在一个或多个阶段引入的非线性误差。将数字校正信号提供给一个或多个级的输出,以消除估计的非线性误差。

著录项

  • 公开/公告号US7602323B2

    专利类型

  • 公开/公告日2009-10-13

    原文格式PDF

  • 申请/专利权人 IAN GALTON;ANDREA PANIGADA;

    申请/专利号US20080080820

  • 发明设计人 ANDREA PANIGADA;IAN GALTON;

    申请日2008-04-04

  • 分类号H03M1/10;

  • 国家 US

  • 入库时间 2022-08-21 19:33:02

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