METHOD AND SYSTEM FOR CREATING ARRAY DEFECT PARETOS USING ELECTRICAL OVERLAY OF BITFAIL MAPS, PHOTO LIMITED YIELD, YIELD, AND AUTO PATTERN RECOGNITION CODE DATA

摘要

A method for creating defect array paretos for semiconductor manufacturing, the method includes: merging a set of ETPLY data {the electrical overlay of bitfail map (BFM) data with inline photo inspection (PLY) data), and auto pattern recognition code (APRC) failure data to create an electrical failure data set along with a set of inline photo inspection defects that caused electrical failures; merging the APRC failure data with wafer final test (WFT) sort data to delineate array failures that are repairable from array failures that are not repairable for the calculation of kill ratios; wherein the merging of the APRC failure data with the WFT sort data is used to create paretos of APRC codes that are array failures that are not repairable; and wherein the merging of the APRC failure data with the WFT sort data is used to create paretos of APRC codes for semiconductor devices that are repairable at wafer final test.