Estimation of Timing Errors in a Time-Interleaved Analog to Digital Converter System

摘要

A method for estimating a relative time difference vector in a group of digitized signals from a time interleaved analog-to-digital module having a plurality of parallel and time interleaved analog-to-digital converters. The method comprises the steps of selecting (S1) one of said digitized signals as a reference signal, calculating (S2-S3) an actual time delay between each of the remaining signals and said reference signal, and subtracting (S4), for each of said remaining signals, an intended interleaving time delay from said time delay. In order for this method to provide the correct estimate, the signal must be bandlimited, not only to the system bandwidth, but to the bandwidth of one ADC. However, given this bandwidth limitation, the estimation is very precise, and therefore enables reconstruction of the digitized signal without feedback.