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Design verification for a switching network logic using formal techniques
Design verification for a switching network logic using formal techniques
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机译:使用形式化技术对交换网络逻辑进行设计验证
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摘要
Formal techniques are applied to industrial design problems such as verification of a circuit design. Initial decisions may include defining properties to verify the design. An abstraction of the design may be generated and model checking applied to the abstraction. Results obtained using these techniques may be extended by performance analysis and/or verification of sequential operations.
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