首页>
外国专利>
Methods, systems, and computer program product for implementing deadlock detection with formal verification techniques in an electronic design
Methods, systems, and computer program product for implementing deadlock detection with formal verification techniques in an electronic design
展开▼
机译:用于在电子设计中使用形式验证技术实现死锁检测的方法,系统和计算机程序产品
展开▼
页面导航
摘要
著录项
相似文献
摘要
Disclosed are methods, systems, and articles of manufacture for implementing deadlock detection with formal verification techniques in an electronic design. These techniques identify one or more inputs that include at least an initial state of an electronic design and identify at least one deadlock candidate by sweeping at least a portion of a state space of the electronic design with formal verification techniques. These techniques then determine whether the at least one deadlock candidate is a real deadlock by using a second formal search with the formal verification techniques.
展开▼