LOW-POWER ANALOG-CIRCUIT ARCHITECTURE FOR DECODING NEURAL SIGNALS

摘要

A microchip for performing a neural decoding algorithm is provided. The microchip is implemented using ultra-low power electronics. Also, the microchip includes a tunable neural decodable filter implemented using a plurality of amplifiers, a plurality of parameter learning filters, a multiplier, a gain and time-constant biasing circuits; and analog memory. The microchip, in a training mode, learns to perform an optimized translation of a raw neural signal received from a population of cortical neurons into motor control parameters. The optimization being based on a modified gradient descent least square algorithm wherein update for a given parameter in a filter is proportional to an averaged product of an error in the final output that the filter affects and a filtered version of its input. The microchip, in an operational mode, issues commands to controlling a device using learned mappings.