APPARATUS FOR REDUCING CACHE LATENCY WHILE PRESERVING CACHE BANDWIDTH IN A CACHE SUBSYSTEM OF A PROCESSOR

摘要

A processor cache memory subsystem includes a cache controller coupled to a tag logic unit. The cache controller may monitor read request resources associated with the cache subsystem and receive read requests for data stored in a data storage array of the cache subsystem. The tag logic unit may determine whether one or more requested address bits match any address tag stored within a tag array of the cache subsystem. The cache controller may, in response to determining the read request resources associated with the cache subsystem are available, selectably send the request for data with an implicit request indication being asserted. In response to determining the read request resources associated with the cache subsystem are not available, the cache controller may send the request for data without an implicit request indication being asserted.