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Cache chain structure to implement high bandwidth low latency cache memory subsystem
Cache chain structure to implement high bandwidth low latency cache memory subsystem
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机译:高速缓存链结构,以实现高带宽,低延迟的高速缓存存储器子系统
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摘要
The inventive cache uses a queuing structure which provides out-of-order cache memory access support for multiple accesses, as well as support for managing bank conflicts and address conflicts. The inventive cache can support four data accesses that are hits per clocks, support one access that misses the L1 cache every clock, and support one instruction access every clock. The responses are interspersed in the pipeline, so that conflicts in the queue are minimized. Non-conflicting accesses are not inhibited, however, conflicting accesses are held up until the conflict clears. The inventive cache provides out-of-order support after the retirement stage of a pipeline.
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