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Integrated circuit with scan-based debugging and debugging method thereof
Integrated circuit with scan-based debugging and debugging method thereof
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机译:具有基于扫描的调试的集成电路及其调试方法
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摘要
An integrated circuit comprises a test interface, an embedded in-circuit emulator, a circuit-under-debugging, and a memory. The embedded in-circuit emulator is used for software debugging via the test interface. The circuit-under-debugging comprises a scan chain dumping states of every delayed flip-flop (DFF) out of the circuit-under-debugging. The memory stores the states from the scan chain and transfers the states to a computer via the test interface.
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