High-speed reduced-output-swing self-biased fully-complementary CMOS comparator with rail-to-rail input common-mode range

摘要

A CMOS comparator having a high-speed reduced-output-swing is provided. The high-speed reduced-output-swing comparator may have a fully complementary CMOS design, be self-biased, and have a rail-to-rail input common-mode range. The self-biasing scheme yields a robust comparator with a low sensitivity to temperature, processing variations, supply-voltage variations, and common-mode input voltages. The fully-complementary design leads to a physically small device with low power consumption. The rail-to-rail input common-mode range leads to a versatile comparator which may take a wide range of inputs. The high-speed reduced-output-swing allows for a quick output response to changes in the input.