Interactive analysis and debugging of a circuit design during functional verification of the circuit design

摘要

While performing functional verification on a circuit design, a verification tool allows a user to analyze the results of a previous functional analysis. The tool may also receive commands for a next verification analysis while performing a current analysis, and it may allow a user to abort a current analysis. Results from a completed analysis may be discarded or saved for viewing by a user while a next verification is performed on the circuit design. This allows a user to continue to debug and analyze the circuit design without having to wait until previous steps in the verification analysis are completed.