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Power gating techniques able to have data retention and variability immunity properties
Power gating techniques able to have data retention and variability immunity properties
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机译:具有数据保留和抗变异性特性的电源门控技术
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摘要
A power gated semiconductor integrated circuit comprises: (1) logic circuit to be power gated, said logic circuit having a virtual ground rail; (2) footer device disposed between said virtual ground rail and a ground rail for reducing power consumption of said logic circuit; and (3) virtual rail voltage clamp disposed electrically in parallel with said footer device for limiting the voltage at the virtual ground rail, the virtual rail voltage clamp comprising at least one NFET. A total of Nf NFETs are connected to the virtual ground rail of the integrated circuit for use as both virtual rail voltage clamps and footer devices. A quantity of Nmax-VC NFETs are scanned and perform the function of voltage clamps and the remaining (Nf−Nmax-VC) NFETs perform power gating. Manufacturing variability immunity and tuning of the variability immunity is achieved by adjusting the quantity Nmax-VC based upon testing of the manufactured integrated circuit.
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机译:一种功率门控的半导体集成电路,包括:(1)要进行功率门控的逻辑电路,所述逻辑电路具有虚拟接地轨;以及(2)用于减少所述逻辑电路的功耗的,位于所述虚拟接地轨和接地轨之间的页脚设备; (3)与所述脚注装置电并联设置的虚拟轨电压钳位器,用于限制虚拟接地轨处的电压,该虚拟轨电压钳位器包括至少一个NFET。总共N f Sub> NFET连接到集成电路的虚拟接地轨,用作虚拟轨电压钳位和脚注设备。扫描N个N max-VC Sub> NFET并执行钳位功能,其余(N f Sub> -N max-VC Sub>) NFET执行功率门控。制造可变性抗扰度和可变性抗扰度的调整是通过根据制造的集成电路的测试调整数量N max-VC Sub>来实现的。
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