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Systolic de-multiplexed finite impulse response filter array architecture for linear and non-linear implementations
Systolic de-multiplexed finite impulse response filter array architecture for linear and non-linear implementations
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机译:用于线性和非线性实现的脉动解复用有限脉冲响应滤波器阵列架构
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摘要
Described is a finite impulse filter response (FIR) filter for use by signal processors. A demultiplexer receives input data samples at an input data rate. The FIR filter includes a plurality of computational units arranged in a systolic array of taps and phases. Each computational unit operates at an array clock rate that is slower than the input data rate. During each array clock cycle, the phases produce a plurality of output data samples that provides an output data rate equal to the input data rate. The FIR filters can thus support an output data rate equal to the input data rate although the input data rate exceeds the maximum clock speed of the processor. The FIR filter can also operate at a reduced array clock speed, while continuing to produce an output data rate equal to the input data rate, to increase the power efficiency of the processor.
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