The impact of alternative encoding techniques on field programmable gate array implementation of sigma-delta modulated ternary finite impulse response filters

摘要

This paper presents the design and synthesis of a single-bit ternary finite impulse response filter with balanced ternary coefficients (ie. -1, 0, +1) implemented in VHDL on small commercial field programmable gate arrays (FPGAs). A comparison is made between implementations based on 2s complement, redundant binary signed digit (RBSD) and canonical signed digit (CSD) encoding techniques. Through simulation, the area and performance of an example filter are analysed using pipelined and non-pipelined modes for all three techniques. The simulation results show that, unlike in the equivalent multi-bit filters, CSD offers no advantages in single-bit sigma-delta modulated (∑△M) systems. Similarly, RBSD occupies twice the area and exhibits much poorer performance compared to a conventional 2s complement representation due to the small symbol size in single-bit systems. These results demonstrate that simple, short word length ∑△M filters will be useful in greatly reducing the number of general-purpose digital multipliers in general purpose digital signal processor applications using FPGA and especially ASIC.