首页> 外国专利> Early high speed serializer-deserializer (HSS)internal receive (Rx) interface for data sampling clock signals on parallel bus

Early high speed serializer-deserializer (HSS)internal receive (Rx) interface for data sampling clock signals on parallel bus

机译:早期的高速串行器/解串器(HSS)内部接收(Rx)接口,用于并行总线上的数据采样时钟信号

摘要

In a method for reading data from a serial data source in a parallel format, data from the serial data source is deserialized by placing a plurality of predefined units of data onto a parallel bus and asserting a deserialization clock when each of the plurality of predefined units is valid on the parallel bus. A delayed clock pulse is generated a predetermined amount of time after each assertion of the deserialization clock. Each delayed pulse is repeated so as to generate an end point repeated clock pulse corresponding to each delayed pulse wherein the predetermined amount of time is an amount of time that ensures that each predefined unit of data on the parallel bus is valid when each end point repeated clock pulse is asserted.
机译:在用于以并行格式从串行数据源读取数据的方法中,通过将多个预定义的数据单元放置在并行总线上并在多个预定义单元中的每个预定义单元时声明反序列化时钟,来对来自串行数据源的数据进行反序列化。在并行总线上有效。在反序列化时钟的每个断言之后的预定时间量内生成延迟的时钟脉冲。重复每个延迟脉冲,以便生成与每个延迟脉冲相对应的端点重复时钟脉冲,其中预定时间量是确保每个端点重复时确保并行总线上每个预定数据单元有效的时间量时钟脉冲有效。

著录项

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号