首页>
外国专利>
Method for early logic mapping during FPGA synthesis
Method for early logic mapping during FPGA synthesis
展开▼
机译:在FPGA合成过程中进行早期逻辑映射的方法
展开▼
页面导航
摘要
著录项
相似文献
摘要
Programming software defining an algorithm that provides improved power, area and frequency predictability of a logic design early in the synthesis flow process, prior to Technology Mapping, without degrading the power, speed or area of the design implementation for PLDs. The method of the algorithm involves performing a high level synthesis of the logic to generate a netlist, performing a multilevel synthesis on the netlist to generate a gate implementation of the netlist; and performing technology mapping on the gate implementation to map the gate implementation to actual resources on the target device. During the high level synthesis of the logic into the netlist, technology mapping is performed on a selected portion of the logic to improve the predictability of the power, area and/or frequency of the logic design without substantially degrading the performance of the power, area and frequency of the logic design.
展开▼