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Systems and methods for reducing static and total power consumption in a programmable logic device
Systems and methods for reducing static and total power consumption in a programmable logic device
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机译:用于减少可编程逻辑器件中的静态功耗和总功耗的系统和方法
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摘要
A method and system for reducing power consumption in a programmable logic device (PLD) is provided. The power consumption may be reduced by preferably continually considering power consumption as a factor in circuit design during the technology mapping, routing, and period following routing of the programmable logic device.
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