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Method of predicting microprocessor lifetime reliability using architecture-level structure-aware techniques

机译:使用体系结构级结构感知技术预测微处理器寿命可靠性的方法

摘要

A method of predicting the lifetime reliability of an integrated circuit device with respect to one or more failure mechanisms includes breaking down the integrated circuit device into structures; breaking down each structure into elements and devices; evaluating each device to determine whether the device is vulnerable to the failure mechanisms and eliminating devices determined not to be vulnerable; estimating, for each determined vulnerable device, the impact of a failure of the device on the functionality of the specific element associated therewith, and classifying the failure into a fatal failure or a non-fatal failure, wherein a fatal failure causes the element employing the given device to fail; determining, for those devices whose failures are fatal, an effective stress degree and/or time; determining one or more of a failure rate and a probability of fatal failure for the devices, and aggregating the same across the structures and the failure mechanisms.
机译:一种针对一个或多个故障机制预测集成电路装置的寿命可靠性的方法,包括将集成电路装置分解成多个结构;将每个结构分解为元素和设备;评估每个设备以确定该设备是否易受故障机制的影响,并消除确定为不易受攻击的设备;对于每个确定的易受攻击的设备,估计该设备的故障对与其相关联的特定元素的功能的影响,并将该故障分类为致命性故障或非致命性故障,其中致命性故障导致采用该故障的元素给定设备发生故障;为那些致命的设备确定有效的应力等级和/或时间;确定设备的故障率和致命故障的概率中的一个或多个,并在结构和故障机制之间进行汇总。

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