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METHOD AND SYSTEM FOR VERIFYING PERFORMANCE OF AN ARRAY BY SIMULATING OPERATION OF EDGE CELLS IN A FULL ARRAY MODEL
METHOD AND SYSTEM FOR VERIFYING PERFORMANCE OF AN ARRAY BY SIMULATING OPERATION OF EDGE CELLS IN A FULL ARRAY MODEL
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机译:通过在全阵列模型中模拟边缘单元的运行来验证阵列性能的方法和系统
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摘要
A method and system for verifying performance of an array by simulating operation of edge cells in a full array model reduces the computation time required for complete design verification. The edge cells of the array (or each subarray if the array is partitioned) are subjected to a timing simulation while the center cells of the array are logically disabled, but remain in the circuit model, providing proper loading. Additional cells are specified for simulation if calculations indicate a worst-case condition due to a non-edge cell. Wordline arrivals are observed to determine worst-case rows for selection. For write operations, the difference between the wordline edges and the data edges is used to locate any non-edge 'outlier' cells. For read operations, the wordline delays are summed with the bitline delays determined from edge column data to locate any outliers.
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