METHODOLOGIES AND TOOL SET FOR IDDQ VERIFICATION, DEBUGGING AND FAILURE DIAGNOSIS

摘要

The present invention relates to quiescent supply current (I00J testing for detecting defects in an integrated circuit. The present invention is based on forming a pair of failing and passing vectors, and iteratively forming a probe vector as the combination of the failing and the passing vectors with additional subsets from the failing vector, for a previous passing probe vector, or additional subsets from the passing vector, for a previous failing probe vector, to converge upon a final pair of vectors differing by a critical bit whose state directly correlates to a defect of the integrated circuit.