Methodologies and tool set for I_DDQ verification, debugging and failure diagnosis

摘要

Quiescent supply current (I_DDQ) verification, prediction, and debugging of low power semiconductor devices are enhanced by I_DDQ defect diagnosis. If all I_DDQ patterns fail verification, per module analysis is performed to sort out potential module design issues or cell constraint issues. For issues of missing constraints, and cell design or implementation issues leading to extra leakage that could be avoided by adding constraints, there are usually I_DDQ patterns that correlate with expectations, and patterns that do not, due to the random nature of unconstrained scan cell values as determined by the pattern generation tool. Differentiating good and bad I_DDQ patterns can identify root causes of I_DDQ issues and additional constraints to fix the bad I_DDQ vectors. These verification procedures are achieving I_DDQ test success and short time to market, as well as significantly faster time to volume and improved yields because of having a higher quality and better-controlled I_DDQ test.