首页> 外国专利> Parallel concatenated zigzag codes with UMTS turbo interleavers

Parallel concatenated zigzag codes with UMTS turbo interleavers

机译:带有UMTS Turbo交错器的并行级联的之字形代码

摘要

An encoder (100) for generating an output codeword based on an input information word, the input information word having fewer bits than the output codeword. The encoder (100) comprising a segmenter (110) for segmenting the input information word into a plurality of coded segments, the segments having bits and comprising a zigzag encoder core (120) for calculating a redundancy bit for a current segment, wherein a redundancy bit of an earlier segment in the order is used for calculating the redundancy bit for the current segment. The encoder (100) further comprising an interleaver (130) for interleaving the bits of the plurality of segments using a first interleaving rule to obtain a first interleaved version and for interleaving the bits of the plurality of segments using a second interleaving rule to obtain a second interleaved version, where the interleaver (130) is designed to generate the first interleaving rule as a predefined interleaving rule obtained by conducting a predefined number of sequenced intermediate sub-steps. The encoder (100) further comprising an output codeword constructor (140) for constructing the output codeword using the input codeword or an interleaved version thereof, a set of first redundancy bits generated by the zigzag encoder core (120) fed by the input codeword or the first interleaved version and a set of second redundancy bits generated by the zigzag encoder core (120) fed by the second interleaved version, wherein the interleaver (130) is adapted to use, as the second interleaving rule, an intermediate interleaving rule obtained by conducting a first sub-step or a number of sub-steps less than the predefined number of sub-steps or an interleaving rule obtained by processing the intermediate interleaving rule in a different manner compared to the remaining sub-steps.
机译:编码器(100),用于基于输入信息字生成输出代码字,该输入信息字的比特数少于输出代码字的比特数。编码器(100)包括用于将输入信息字分割成多个编码段的分段器(110),这些段具有位并且包括用于计算当前段的冗余位的之字形编码器核(120),其中冗余该顺序中较早的段的比特用于计算当前段的冗余比特。编码器(100)还包括交织器(130),用于使用第一交织规则对多个片段的比特进行交织以获得第一交织版本,并且使用第二交织规则对用于多个片段的比特进行交织以获得交织。第二交织版本,其中交织器(130)被设计为生成第一交织规则,作为通过进行预定数量的顺序中间子步骤而获得的预定交织规则。编码器(100)还包括用于使用输入码字或其交错版本来构造输出码字的输出码字构造器(140),由之字形编码器核(120)由输入码字馈送的一组第一冗余比特或第一交织版本和由第二交织版本馈送的之字形编码器核心(120)生成的第二冗余位的集合,其中,交织器(130)适用于将通过以下方式获得的中间交织规则用作第二交织规则:进行第一子步骤或少于预定数量的子步骤的子步骤或通过与其余子步骤相比以不同方式处理中间交织规则而获得的交织规则。

著录项

  • 公开/公告号EP1926215B1

    专利类型

  • 公开/公告日2009-05-27

    原文格式PDF

  • 申请/专利权人 NTT DOCOMO INC;

    申请/专利号EP20060024548

  • 发明设计人 BAUCH GERHARD;KUSUME KATSUTOSHI;

    申请日2006-11-27

  • 分类号H03M13/27;H03M13/29;

  • 国家 EP

  • 入库时间 2022-08-21 19:17:15

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