首页> 外国专利> Concatenated codes combining Reed-Solomon codes, LDPC codes and parity codes for encoding/decoding devices

Concatenated codes combining Reed-Solomon codes, LDPC codes and parity codes for encoding/decoding devices

机译:结合了Reed-Solomon码,LDPC码和奇偶校验码的级联码,用于编码/解码设备

摘要

An error correction device error corrects without increasing the circuit scale. An encoder includes: a first ECC encoder (235) which interleaves a data string into n (n ≥ 2) blocks of data strings at every m (m ≥ 2) bits, and adds the error correction code parity; a parity encoder (234) which creates a parity bit at every plurality of bits of the error correction code word, and adds the parity bit to said error correction code word; and a second ECC encoder (220), which generates a second error correction encoding, which is a linear encoding using iterative decoding. Concatenated type encoded data, where a parity bit is added to every plurality of bits, is created, so an increase of circuit scale can be prevented even if a data string is interleaved into a plurality of blocks and error correction code parity is generated. The device may be applied, for example, to a long sector type hard disk.
机译:纠错装置在不增加电路规模的情况下进行纠错。编码器包括:第一ECC编码器(235),其以每m(m≥2)个比特将数据串交织到n(n≥2)个数据串块中,并添加纠错码奇偶校验;奇偶校验编码器(234),其在纠错码字的每多个比特处创建一个奇偶校验位,并将奇偶校验位添加到所述纠错码字;第二ECC编码器(220),其产生第二纠错编码,该第二纠错编码是使用迭代解码的线性编码。由于创建了将每个奇偶校验位添加一个奇偶校验位的级联类型编码数据,因此即使将数据串插入多个块中并生成纠错码奇偶校验,也可以防止电路规模的增加。该设备可以应用于例如长扇区型硬盘。

著录项

  • 公开/公告号EP2086114A2

    专利类型

  • 公开/公告日2009-08-05

    原文格式PDF

  • 申请/专利权人 FUJITSU LIMITED;

    申请/专利号EP20080170099

  • 发明设计人 KANAOKA TOSHIKAZU;ITO TOSHIO;

    申请日2008-11-27

  • 分类号H03M13/29;H03M13/11;H03M13/09;H03M13/15;

  • 国家 EP

  • 入库时间 2022-08-21 19:15:10

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