OVERLAY VERNIER AND A METHOD FOR FORMING THE SAME, CAPABLE OF PREVENTING DEFORMATION OF OVERLAY VERNIER FROM THERMAL, PHYSICAL, AND CHEMICAL STRESS

摘要

PURPOSE: An overlay vernier and a method for forming the same are provided to improve the characteristic of the semiconductor device and manufacture a high performance semiconductor by preventing deformation of overlay and misalignment of a pattern.;CONSTITUTION: In an overlay vernier and a method for forming the same, an overlay vernier includes a mother vernier, and the mother vernier includes a plurality of a unit mother vernier patterns connected to a plurality of vernier contacts. The overlay vernier formation method is comprised of the steps: an insulating layer(110) is deposited on a semiconductor substrate(100) including an infrastructure; the plural vernier contacts(120) are formed by patting the insulating layer; and the plural mother vernier pattern(130) connected to the plural vernier contacts are formed.;COPYRIGHT KIPO 2010